arXiv eess.SY / cs.AR: TinyML / edge inference
A Time-Multiplexed Spiking Neural Network Accelerator with Pipelined Readout for FPGA Inference
FPGA 추론을 위한 파이프라인 읽기 기능을 갖춘 시분할 스파이킹 신경망 가속기
No write-up yet — this entry is still just the auto-fetched hook. Aaron's own summary (200–500 words) will replace this note once he's written it.